memory module specifcations kvr667d2d4f5k2/8g 8gb (4gb 512m x 72-bit x 2 pcs.) pc2-5300 cl5 ecc 240-pin fbdimm kit kingston.com document no. valueram0530-001.a00 01/11/07 page 1 description valuerams kvr667d2d4f5k2/8gb is a kit of two 512m x 72-bit 4gb (4096mb) pc2-5300 cl5 sdram (synchronous dram) fully buffered ecc dual rank memory modules. total kit capacity is 8gb (8192mb). each module is based on eighteen stacked 512m x 4-bit (thirty-six 256m x 4-bit) 667mhz ddr2 fbga components. each module also includes an amb device (advanced memory buffer). the electrical and mechanical specifcations are as follows: specifications fbdimm module 240-pin jedec standard r/c h or e memory organization 2 rank of x4 devices ddr2 dram interface sstl_18 ddr2 speed grade 667 mbps cas latency 5-5-5 module bandwidth 5.3 gb/s dram vdd = vddq = 1.8v amb vcc = vccfbd = 1.5v eeprom vddspd = 3.3v (typical) heat spreader full dimm heat spreader (fdhs) pcb height 30.35mm, double-side rohs compliant continued >>
continued valueram kingston.com document no. valueram0530-001.a00 01/11/07 page 2 continued >> ddr2 240-pin fbdimm pinout : pin # front side pi n # back side pin # front side pin # back side pin # front side pi n # back side pin # front side pin # ba ck side 1 v dd 121 v dd 31 pn 31 51 sn36 1p n9 18 1s n9 91 ps 9 21 1s s9 2 v dd 122 v dd 32 pn 3 15 2s n3 62 v ss 18 2 v ss 92 v ss 21 2 v ss 3 v dd 123 v dd 33 v ss 15 3 v ss 63 pn10 18 3 sn10 93 ps 52 13 ss 5 4 v ss 124 v ss 34 pn 41 54 sn46 4p n10 18 4s n1 0 94 ps 5 21 4s s5 5 v dd 125 v dd 35 pn 4 15 5s n4 65 v ss 18 5 v ss 95 v ss 21 5 v ss 6 v dd 126 v dd 36 v ss 15 6 v ss 66 pn11 18 6s n1 19 6p s6 21 6s s6 7 v dd 127 v dd 37 pn 51 57 sn56 7p n1 1 18 7s n1 1 97 ps 6 21 7s s6 8 v ss 128 v ss 38 pn 5 15 8s n5 68 v ss 18 8 v ss 98 v ss 21 8 v ss 9 v cc 129 v cc 39 v ss 15 9 v ss key 99 ps 72 19 ss 7 10 v cc 130 v cc 40 pn131 60 sn13 69 v ss 18 9 v ss 100p s7 22 0s s7 11 v ss 131 v ss 41 pn13 16 1s n1 3 70 ps 01 90 ss01 01 v ss 22 1 v ss 12 v cc 132 v cc 42 v ss 16 2 v ss 71 ps 0 191 ss0 102p s8 22 2s s8 13 v cc 133 v cc 43 v ss 16 3 v ss 72 v ss 19 2 v ss 103p s8 22 3s s8 14 v ss 134 v ss 44 rfu* 16 4r fu*7 3p s1 19 3s s1 104 v ss 22 4 v ss 15 v tt 135 v tt 45 rfu*1 65 rfu* 74 ps 1 194 ss1 105 rfu ** 22 5 rfu ** 16 vid1 136v id 04 6 v ss 16 6 v ss 75 v ss 19 5 v ss 106 rfu ** 22 6 rfu ** 17 reset 137 dnu/m_ te st 47 v ss 16 7 v ss 76 ps 21 96 ss21 07 v ss 22 7 v ss 18 v ss 138 v ss 48 pn121 68 sn12 77 ps 2 197 ss2 108 v dd 22 8s ck 19 rfu ** 139 rfu ** 49 pn12 16 9s n1 2 78 v ss 19 8 v ss 109 v dd 22 9s ck 20 rfu ** 140 rfu ** 50 v ss 17 0 v ss 79 ps 31 99 ss31 10 v ss 23 0 v ss 21 v ss 141 v ss 51 pn 61 71 sn68 0p s3 200 ss3 111 v dd 23 1 v dd 22 pn01 42 sn05 2p n6 17 2s n6 81 v ss 20 1 v ss 11 2 v dd 23 2 v dd 23 pn 0 143s n0 53 v ss 17 3 v ss 82 ps 42 02 ss41 13 v dd 23 3 v dd 24 v ss 144 v ss 54 pn 71 74 sn78 3p s4 203 ss4 11 4 v ss 23 4 v ss 25 pn11 45 sn15 5p n7 17 5s n7 84 v ss 20 4 v ss 11 5 v dd 23 5 v dd 26 pn 1 146s n1 56 v ss 17 6 v ss 85 v ss 20 5 v ss 11 6 v dd 23 6 v dd 27 v ss 147 v ss 57 pn 81 77 sn88 6r fu*2 06 rfu*1 17 v tt 23 7 v tt 28 pn21 48 sn25 8p n8 17 8s n8 87 rfu*2 07 rfu* 11 8s a2 238 vddspd 29 pn 2 149s n2 59 v ss 17 9 v ss 88 v ss 20 8 v ss 11 9s da 23 9s a0 30 v ss 150 v ss 60 pn 91 80 sn98 9 v ss 20 9 v ss 120s cl 24 0s a1 90 ps 92 10 ss9 rfu = reserved future use. * these pin positions are reserved for forwarded clo cks to be used in future module implement ations ** these pin positions are reserved for future architecture flexibility 1) t he following signals are c rc b it s and t hus appear o ut of the normal sequence: pn12/pn1 2 , sn12/sn12 , pn13/pn13 , sn13/sn13 , ps9/ps9 , ss9/ss 9
continued valueram kingston.com document no. valueram0530-001.a00 01/11/07 page 3 continued >> dimm connector pin description: pin name pin description count sck system clock input, positive line 1 1 sck system clock input, negative line 1 1 4 1 s e n i l e v i t i s o p , a t a d d n u o b h t r o n y r a m i r p ] 0 : 3 1 [ n p pn 4 1 s e n i l e v i t a g e n , a t a d d n u o b h t r o n y r a m i r p ] 0 : 3 1 [ 0 1 s e n i l e v i t i s o p , a t a d d n u o b h t u o s y r a m i r p ] 0 : 9 [ s p ps 0 1 s e n i l e v i t a g e n , a t a d d n u o b h t u o s y r a m i r p ] 0 : 9 [ 4 1 s e n i l e v i t i s o p , a t a d d n u o b h t r o n y r a d n o c e s ] 0 : 3 1 [ n s sn 4 1 s e n i l e v i t a g e n , a t a d d n u o b h t r o n y r a d n o c e s ] 0 : 3 1 [ 0 1 s e n i l e v i t i s o p , a t a d d n u o b h t u o s y r a d n o c e s ] 0 : 9 [ s s ss 0 1 s e n i l e v i t a g e n , a t a d d n u o b h t u o s y r a d n o c e s ] 0 : 9 [ 1 t u p n i k c o l c ) d p s ( t c e t e d e c n e s e r p l a i r e s l c s sda spd dat a input / output 1 3 b m a e h t n i r e b m u n m m i d e h t t c e l e s o t d e s u o s l a , s t u p n i s s e r d d a d p s ] 0 : 2 [ a s vid[1:0] vo lt age id: these pins must be unconnected for ddr2-based fully buf fered dimms vid[0] is v dd value: open = 1.8 v , gnd = 1.5 v ; vid[1] is v cc value: open = 1.5 v , gnd = 1.2 v 2 reset amb reset signal 1 rf u reserved for future use 2 16 v cc 8 ) t l o v 5 . 1 ( r e w o p e c a f r e t n i l e n n a h c b m a d n a r e w o p e r o c b m a v dd 4 2 ) t l o v 8 . 1 ( r e w o p o / i m a r d b m a d n a r e w o p m a r d v tt dram address/command/clock t ermination power (v dd /2) 4 v ddspd spd powe r 1 v ss ground 80 dnu/m_t est the dnu/m_t est pin provides an exter nal connection on r/cs a-d for testing the margin of vr ef which is produced by a voltage divider on the module. it is not intended to be used in normal system operation and must not be connected (dnu) in a system. this test pin may have other features on future card designs and if it does, will be included in this specification at that time. 1 1 t otal 240 1. system clock signals sck and sck switch at one half the dram ck/ck frequency 2. eight pins reserved for forwarded clocks, eight pi ns reserved for future architecture flexibility absolute maximum ratings 09 5 c amb device operating temperature (ambient) 01 10 c symbol parameter min max units v in , v ou t vo ltage on any pin relative to v ss -0.31 .75 v v cc vo ltage on v cc pin rela tive to v ss -0.31 .75 v v dd vo ltage v dd pin rela tive to vss -0.5 2.3 v v tt vo ltage on v tt pin rela tive t o v ss -0.5 2.3 v t stg st orage temper at ur e -551 00 c t case ddr2 sdram device operat ing temperature (ambient) note: (1) above 85c dram case temperature the a uto-refresh command interval has to be reduced to trefi = 3.9 s. 95 (1)
continued valueram kingston.com document no. valueram0530-001.a00 01/11/07 page 4 continued >> functional block diagram : s 0 dq s0 vs s notes: 1 . dq-to-i/o wiring may be changed within a nibbl e 2 . there are two physical copies of each address/command/control 3. there are four physical copies of each cloc k dq s 0 dqs9 dq4 dq5 dq6 dq7 dqs 9 dqs1 dq 8 dq 9 dq 10 dq 11 dm d1 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dqs 1 dqs10 dq 12 dq 13 dq 14 dq 15 dqs 10 dqs2 dq1 6 dq1 7 dq1 8 dq1 9 dm d2 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dqs 2 dqs11 dq 20 dq 21 dq 22 dq 23 dqs 11 dqs3 dq 24 dq 25 dq 26 dq 27 dm d3 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dqs 3 dqs12 dq2 8 dq2 9 dq3 0 dq3 1 dqs 12 dqs4 dq3 2 dq3 3 dq3 4 dq3 5 dm d4 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dqs 4 dqs13 dq 36 dq 37 dq 38 dq 39 dqs 13 dqs5 dq4 0 dq4 1 dq4 2 dq4 3 dm d5 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dq s 5 dqs14 dq 44 dq 45 dq 46 dq 47 dqs 14 dqs6 dq4 8 dq4 9 dq5 0 dq5 1 dm d6 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dq s 6 dqs15 dq 52 dq 53 dq 54 dq 55 dqs 15 dqs7 dq5 6 dq5 7 dq5 8 dq5 9 dm d7 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dq s 7 dqs16 dq6 0 dq6 1 dq6 2 dq6 3 dqs 16 dqs8 cb 0 cb 1 cb 2 cb 3 dm d8 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dq s 8 dqs17 cb 4 cb 5 cb 6 cb 7 dqs 17 a0 serial p d a1 a2 sa0s a1 sa2 sda scl wp dq0 dq1 dq2 dq3 dm d0 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs a m b pn0-pn1 3 pn 0- pn 13 ps0-ps 9 ps 0-ps 9 ss 0- ss 9 ss 0- ss 9 we ( all sdrams ) ck/c k (all sdrams ) ba 0-ba2 (all sdrams ) a0-a15 (all sdrams ) ra s (all sdrams ) ca s ( all sdrams ) dm d19 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d20 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d21 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d22 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d23 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d24 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d25 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d26 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d1 8 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d10 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d1 1 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d12 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d13 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d14 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d15 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d16 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d17 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d9 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s dm d28 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d29 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d30 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d31 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d32 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d33 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d34 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d35 cs dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs dm d27 cs dq s i/o 0 i/o 1 i/o 2 i/o 3 dq s s 1 odt -> odt0 (all sdrams ) v ss d0 -d 35, amb d0 -d 35, spd , d0 -d 35 v re f sp d, a mb v dd v ddsp d am b v cc v tt te rm inators v tt all address/command/control/clock sn0-sn13 sn 0-sn 13 cke0 -> cke (d0-d17 ) s 0 -> c s ( d0-d17 ) cke1 -> cke ( d18-d35) s 1 -> cs (d18-d35) amb sc l sd a sa 1-sa 2 reset sc k/ sc k sa 0 825 33
continued valueram kingston.com document no. valueram0530-001.a00 01/11/07 page 5 continued >> architecture: advanced memory buffer pin description: pin name pin description count fb-dimm channel signals 99 1 e n i l e v i t i s o p , t u p n i k c o l c m e t s y s k c s sck 1 e n i l e v i t a g e n , t u p n i k c o l c m e t s y s 4 1 s e n i l e v i t i s o p , a t a d d n u o b h t r o n y r a m i r p ] 0 : 3 1 [ n p pn 4 1 s e n i l e v i t a g e n , a t a d d n u o b h t r o n y r a m i r p ] 0 : 3 1 [ 0 1 s e n i l e v i t i s o p , a t a d d n u o b h t u o s y r a m i r p ] 0 : 9 [ s p ps 0 1 s e n i l e v i t a g e n , a t a d d n u o b h t u o s y r a m i r p ] 0 : 9 [ 4 1 s e n i l e v i t i s o p , a t a d d n u o b h t r o n y r a d n o c e s ] 0 : 3 1 [ n s sn 4 1 s e n i l e v i t a g e n , a t a d d n u o b h t r o n y r a d n o c e s ] 0 : 3 1 [ 0 1 s e n i l e v i t i s o p , a t a d d n u o b h t u o s y r a d n o c e s ] 0 : 9 [ s s ss 0 1 s e n i l e v i t a g e n , a t a d d n u o b h t u o s y r a d n o c e s ] 0 : 9 [ fbdrest o an external precision cali 1 c c v o t d e t c e n n o c r o t s i s e r n o i t a r b ddr2 interface signals 17 5 dqs[8:0] da ta s trobes, positive lines 9 dq s [8:0] dat a s trobes, negative lines 9 dqs[17:9]/dm[8:0 ]d at a s trobes (x4 dram only), positive li nes. these signals are driven low to x8 dram on writes .9 dq s 9 s e n i l e v i t a g e n , ) y l n o m a r d 4 x ( s e b o r t s a t a d ] 9 : 7 1 [ dq[63:0 ]d ata 64 cb[7:0]c heckbits 8 2 3 d n a m m o c e g r a h c - e r p e h t f o t r a p s i 0 1 a . s e s s e r d d a b ] 0 : 5 1 [ a , a ] 0 : 5 1 [ a ba[2:0]a, ba[2:0] bb ank addresses 6 ras a, ras bp art of command, with cas , we , and c s 2 . ] 0 : 1 [ cas a, cas bp art of command, with ras , we , and c s 2 . ] 0 : 1 [ we a, we bp art of command, with ras , ca s , and cs 2 . ] 0 : 1 [ odt a, odtb on-die termination enable 2 cke[1:0]a, cke[1:0]bc lock enable (one per rank) 4 cs [1:0]a, cs [1:0]bc hip select (one per rank) 4 clk[3:0] clk[1:0] used o n 9 and 1 8 device dimms, clk[3:0] u se d on 36 device dimms. clk[3:2] should b e out- put disabled when not in use. 4 clk [3:0] negative lines for clk[3:0] 4 1 . 8 1 c _ c r d d d n a 8 1 b _ c r d d r o f n i p n r u t e r n o m m o c : n o i t a s n e p m o c r d d 4 1 c _ c r d d 1 4 1 c _ c r d d n i p n r u t e r n o m m o c o t d e t c e n n o c r o t s i s e r : n o i t a s n e p m o c r d d 8 1 b _ c r d d 1 4 1 c _ c r d d n i p n r u t e r n o m m o c o t d e t c e n n o c r o t s i s e r : n o i t a s n e p m o c r d d 8 1 c _ c r d d ddrc_b12 ddr compensation: resistor connected to v ss 1 ddrc_c12 ddr compensation: resistor connected to v dd 1
continued valueram kingston.com document no. valueram0530-001.a00 01/11/07 page 6 continued >> spd bus interface signal s 5 1 t u p n i k c o l c ) d p s ( t c e t e d e c n e s e r p l a i r e s l c s sda spd dat a input / output 1 3 b m a e h t n i r e b m u n m m i d e h t t c e l e s o t d e s u o s l a , s t u p n i s s e r d d a d p s ] 0 : 2 [ a s miscellaneous signal s 16 3 pllt st op ll clock observability output 1 1 . c c v o t r e t l i f s s a p w o l h t i w d e i t . l l p e h t r o f c c v g o l a n a l l p a c c v vssaplla nalog vss for the pll. t ied to ground on the amb die. do not tie to ground on the dimm .1 test_pin# leave floating on the dimm 6 testlo_pin# t ie to ground on the dimm 2 5 1 . m m i d n o r e f f u b s a y t i l a n o i t c n u f t e s o t d n u o r g o t e i t c n u f b rese t amb reset signa l 1 nc no connect. many nc are connected to vdd on the dimm, to lower the impedance of the vdd power islands. 12 9 rf ur eserved for future use 18 power/ground signal s 21 3 v cc amb core power (1.5 v olt) 24 v ccfbd 8 ) t l o v 5 . 1 ( r e w o p o / i l e n n a h c b m a v dd 4 2 ) t l o v 8 . 1 ( r e w o p o / i m a r d b m a v ddsp d spd power (3.3 v olt ) 1 v ss ground 15 6 5 5 6 l a t o t 1. system clock signals sck and sc k switch at one half the dram ck/ck frequenc y. 2. testlo_ab20 and testlo_ac20 should be configured for debug purposes on prototyp e dimms: each pin should have a zero ohm resistor pulldown to ground, and an unpopulated resistor pul lup to vcc. these resistors can be replaced on production dimms with a direct connection to ground. advanced memory buffer pin description:
continued valueram kingston.com document no. valueram0530-001.a00 01/11/07 page 7 package dimensions: unit s: inches (millimeters) technology amb ad v anced memory buffer det ail a 0.047 (1.19) 0.042 (1.06) 0.042 (1.06) 45x 0.0071(0.18) (unit s = millimeters)
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